1. Field of the Invention
This invention relates to the field of portable communications and specifically to a data transceiver circuit which aligns the transitions of a receiver internal data clock with the transitions of a received data signal.
2. Description of the Prior Art
Portable radio transceivers are used in several facets of communications technology. Portable data transceivers can be found in paging systems, and two-way communications systems such as those used by police and other public servants. Recently portable radio transceivers have found use in portable data terminals which are used to communicate with a host computer. Portable data terminals of this type can provide on-site computer diagnostics of a second host computer.
Most devices which are used for data communications are operated in a synchronous mode, that is, the local clock signal used to operate the portable data terminal is phase compensated so that the transitions of the local clock signal are aligned with the transitions of an incoming data signal.
Several well-known techniques have been developed for synchronizing a local clock to a received data signal. One common technique advances or retards the local clock signal by adding on pulses from a signal fed to a frequency divider chain which provides a local signal. Another technique for clock recovery utilizes a programmable divider coupled to a reference clock signal. The recovered clock signal is compared to the received data signal and the divider is programmably altered to shift the phase of the recovered clock. This latter technique for phase adjustments is described in a U.S. Pat. No. 4,400,817 issued Aug. 23, 1983 entitled "Method and Means of Clock Recovery in a Received Stream of Digital Data" by Terrence E. Sumner and assigned to the assignee of the present invention.
The above-mentioned techniques for clock recovery operate effectively in most circumstances. However, these techniques require a relatively large amount of time to acquire a recovered clock signal in the presence of data bias distortion occurring in the limiter stage and phase ambiguities. In many situations a phase-ambiguity may exist and the phase compensation circuit may effect an improper phase adjustment resulting in an extended time required to achieve data synchronization.